71M6531D_10 Datasheet, PDF (49/120 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
EECTRL Byte Written
READ
SCLK (output)
CNT Cycles (8 shown)
INT5
SDATA (input)
D7
D6
D5
D4
D3
D2
D1
D0
SDATA output Z
(HiZ)
BUSY (bit)
Figure 13: 3-Wire Interface. Read Command.
EECTRL Byte Written
Write -- No HiZ
SCLK (output)
INT5 not issued
EECTRL Byte Written
CNT Cycles (0 shown)
Write -- HiZ
SCLK (output)
INT5 not issued
CNT Cycles (0 shown)
SDATA (output)
D7
SDATA (output)
SDATA output Z
(LoZ)
SDATA output Z
(HiZ)
BUSY (bit)
BUSY (bit)
Figure 14: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written
Write -- With HiZ and WFR
SCLK (output)
CNT Cycles (6 shown)
SDATA (out/in)
SDATA output Z
D7
D6
D5
D4
D3
D2
(From 6520)
(LoZ)
BUSY
(From EEPROM)
(HiZ)
BUSY (bit)
Figure 15: 3-Wire Interface. Write Command when HiZ=1 and WFR=1
INT5
READY
1.5.15 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
locations. It is also able to send commands to the MPU. The interface to the slave port consists of the
PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3
to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the SPE bit.
A typical SPI transaction is as follows. While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. A transaction consists of
an 8-bit command, a 16-bit address and then one or more bytes of data. The transaction ends when
PCSZ is raised. Some transactions may consist of a command only.
The last SPI command and address (if part of the command) are available to the MPU in registers
SP_CMD and SP_ADDR.
The SPI port supports data transfers at 1 Mb/s in mission mode and 16 kb/s in brownout mode. The SPI
commands are described in Table 49 and in Figure 16 illustrate the SPI Interface read and write timing.
v1.3
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