W78E516DDG Datasheet, PDF (76/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
Clock Period
Clock High
Clock Low
TCP
25
Tch
10
Tcl
10
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
Address Valid to ALE Low
TAAS
1 TCP-Δ
Address Hold from ALE Low
TAAH
1 TCP-Δ
ALE Low to PSEN Low
TAPL
1 TCP-Δ
PSEN Low to Data Valid
TPDA
-
Data Hold after PSEN High
TPDH
0
Data Float after PSEN High
TPDZ
0
ALE Pulse Width
TALW
2 TCP-Δ
PSEN Pulse Width
TPSW
3 TCP-Δ
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
-
-
-
TYP.
-
-
-
-
-
-
2 TCP
3 TCP
-
-
-
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
nS
2
nS
3
nS
3
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
Data Read Cycle
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
SYMBOL
TDAR
TDDA
TDDH
TDDZ
TDRD
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP-Δ
-
0
0
6 TCP-Δ
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP+Δ
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
ITEM
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
TDAW
TDAD
TDWD
TDWR
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP-Δ
1 TCP-Δ
1 TCP-Δ
6 TCP-Δ
TYP.
-
-
-
6 TCP
MAX.
3 TCP+Δ
-
-
-
UNIT
nS
nS
nS
nS
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