W78E516DDG Datasheet, PDF (62/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
grammable 9th bit (TB8) and a stop bit (1). The 9th bit received is put into RB8. The baud rate is pro-
grammable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in PCON
SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at S6P2
following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at S6P2 fol-
lowing the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the di-
vide by 16 counters, and not directly to the write to SBUF signal. After all 9 bits of data are transmitted,
the stop bit is transmitted. The TI flag is set in the S6P2 state after the stop bit has been put out on
TxD pin. This will be at the 11th rollover of the divide by 16 counters after a write to SBUF. Reception
is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the de-
tection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sam-
pling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16
counters is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by
16 counters. The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection
is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th coun-
ter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve
the noise rejection feature of the serial port.
Fosc/2
1/2
SMOD 0 1
1/16
1/16
SAMPLE
1-To-0
DETECTOR
RXD
Write to
SBUF
TX START
TX CLOCK
Transmit Shift Register
1
TB8
Internal
Data Bus
0
STOP
D8
PARIN
START
LOAD
SOUT
CLOCK
TXD
TX SHIFT
Serial
Controllor ^TI
RX CLOCK
RI
TX START
LOAD SBUF
RX SHIFT
Serial Interrupt
Read SBUF
BIT
DETECTOR
CLOCK PAROUT
SBUF
SIN
D8
RB8
Receive Shift Register
Internal
Data Bus
Figure 16- 3 Serial port mode 2
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. Af-
ter shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and
RI is set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
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