W78E516DDG Datasheet, PDF (25/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
Serial Port Control
Bit: 7
6
5
4
3
2
1
0
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT NAME FUNCTION
7 SM0/FE Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON
SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE condition.
6 SM1
Serial Port mode select bit 1. See table below.
5 SM2
Multiprocessor communication mode enable.
The function of this bit is dependent on the serial port mode.
Mode 0: No effect.
Mode 1: Checking valid stop bit.
0 = Reception is always valid no matter the logic level of stop bit.
1 = Reception is ignored if the received stop bit is not logic 1.
Mode 2 or 3: For multiprocessor communication.
0 = Reception is always valid no matter the logic level of the 9th bit.
1 = Reception is ignored if the received 9th bit is not logic 1.
4 REN
Receive enable:
0: Disable serial reception.
1: Enable serial reception.
3 TB8
This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared
by software as desired.
2 RB8
In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is
the stop bit that was received. In mode 0 it has no function.
1 TI
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or at the beginning of the stop bit in all other modes during serial
transmission. This bit must be cleared by software.
0 RI
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or halfway through the stop bits time in the other modes during serial
reception. However the restrictions of SM2 apply to this bit. This bit can be
cleared only by software.
Mode
0
1
2
3
SM0
0
0
1
1
SM1
0
1
0
1
SM1, SM0: Mode Select bits:
Description
Length Baud Rate
Synchronous
8
Tclk divided by 4 or 12
Asynchronous
10 Variable
Asynchronous
11 Tclk divided by 32 or 64
Asynchronous
11 Variable
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Publication Release Date: Feb 15, 2011
Revision A09