W78E516DDG Datasheet, PDF (49/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled inter-
rupts are polled and their priority is resolved. If certain conditions are met then the hardware will exe-
cute an internally generated LCALL instruction which will vector the process to the appropriate inter-
rupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IE, IP, XICON registers and is not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is re-
peated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt flag
is active in one cycle but not responded to, and is not active when the above conditions are met, the
denied interrupt will not be serviced. This means that active interrupts are not remembered; every poll-
ing cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate ser-
vice routine. This may or may not clear the flag which caused the interrupt. In case of Timer interrupts,
the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the appropriate timer
service routine. In case of external interrupt, /INT0 and /INT1, the flags are cleared only if they are
edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. In the case of Timer
2 interrupt, the flags are not cleared by hardware. The hardware LCALL behaves exactly like the soft-
ware LCALL instruction. This instruction saves the Program Counter contents onto the Stack, but does
not save the Program Status Word PSW. The PC is reloaded with the vector address of that interrupt
which caused the LCALL. These address of vector for the different sources are as shown on below
table. The vector table is not evenly spaced; this is to accommodate future expansions to the device
family.
Execution continues from the vectored address till an RETI instruction is executed. On execution of
the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what is was after the hard-
ware LCALL, if the execution is to return to the interrupted program. The processor does not notice
anything if the stack contents are modified and will proceed with execution from the address put back
into PC. Note that a RET instruction would perform exactly the same process as a RETI instruction,
but it would not inform the Interrupt Controller that the interrupt service routine is completed, and
would leave the controller still thinking that the service routine is underway.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IE.
The IE register also contains a global disable bit, EA, which disables all interrupts at once.
Each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing
bits in the IP registers. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two requests of different priority levels are
received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence deter-
mines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking
is only used to resolve simultaneous requests of the same priority level.
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Publication Release Date: Feb 15, 2011
Revision A09