W78E516DDG Datasheet, PDF (54/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
14.2.4 Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply
freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count
registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0
control bits ^C/T , GATE, TR0, ^INT0 and TF0. The TL0 can be used to count clock cycles (clock/12) or
1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle counter
(clock/12) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is used in cases
where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used in Modes 0, 1
and 2, but its flexibility is somewhat limited. While its basic functionality is maintained, it no longer has
control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer/counter
and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by switching it
out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port.
Fosc
1/12
T0=P3.4
TR0=TCON.4
C/T=TMOD.2
0
1
TL0
0
7
TF0
Interrupt
GATE=TMOD.3
INT0=P3.2
TR1=TCON.6
TH0
0
7
Figure 14-3 Timer/Counter Mode 3
TF1
Interrupt
14.3 Timer/Counter 2
Timer/Counter 2 is a 16 bit counter. Timer/Counter 2 is equipped with a capture/reload capability. As
with the Timer 0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling
the clock, and in defining the operating mode. The clock source for Timer/Counter 2 may be selected
for either the external T2 pin (C/T2 = 1) or the crystal oscillator, which is divided by 12 (C/T2 = 0). The
clock is then enabled when TR2 is a 1, and disabled when TR2 is a 0.
14.3.1 Capture Mode
The capture mode is enabled by setting the ^{CP / RL2} bit in the T2CON register to a 1. In the capture
mode, Timer/Counter 2 serves as a 16 bit up counter. When the counter rolls over from 0FFFFh to
0000h, the TF2 bit is set, which will generate an interrupt request. If the EXEN2 bit is set, then a nega-
tive transition of T2EX pin will cause the value in the TL2 and TH2 register to be captured by the
RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will
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