W78E516DDG Datasheet, PDF (21/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
Frame Error (FE) status flag.
5-
Reserved
4 POR 0: Cleared by software.
1: Set automatically when a power-on reset has occurred.
3 GF1
General purpose user flags.
2 GF0
General purpose user flags.
1 PD
1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are
stopped and program execution is frozen.
0 IDL
1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock stopped,
so program execution is frozen. But the clock to the serial, timer and interrupt
blocks is not stopped, and these blocks continue operating.
Timer Control
Bit: 7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
BIT NAME FUNCTION
7 TF1
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared auto-
matically when the program does a timer 1 interrupt service routine. Software can
also set or clear this bit.
6 TR1
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter on
or off.
5 TF0
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared auto-
matically when the program does a timer 0 interrupt service routine. Software can
also set or clear this bit.
4 TR0
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on
or off.
3 IE1
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on
INT1. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
2 IT1
Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level
triggered external inputs.
1 IE0
Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected
on INT0 . This bit is cleared by hardware when the service routine is vectored to
only if the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
0 IT0
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
Timer Mode Control
Bit: 7
6
5
4
3
2
1
0
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Publication Release Date: Feb 15, 2011
Revision A09