W78E516DDG Datasheet, PDF (50/90 Pages) Nuvotem Talema – 8-BIT MICROCONTROLLER

W78E516D/W78E058D Data Sheet
Table below summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and external interrupt may wake up the CPU from Power Down mode.
Source
Flag
External Interrupt 0 IE0
Timer 0 Overflow
TF0
External Interrupt 1 IE1
Timer 1 Overflow
TF1
Serial Port
Timer 2 Over-
flow/Match
External Interrupt 2
RI + TI
TF2
XICON
External Interrupt 3 XICON
Vector Enable bit Flag
Arbitration
address
cleared by ranking
0003H
000BH
0013H
001BH
0023H
002BH
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
ET2 (IE.5)
Hardware,
software
Hardware,
software
Hardware,
software
Hardware,
software
Software
Software
1(highest)
2
3
4
5
6
0033H
003BH
EX2
(XICON.2)
EX3
(XICON.6)
Hardware,
software
Hardware,
software
7
8(lowest)
Power-
down
wakeup
Yes
No
Yes
No
No
No
Yes
Yes
Table 13- 2 Summary of interrupt sources
13.4 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the in-
terrupt and the instruction underway. In the case of external interrupts INT0 and INT1 , they are sam-
pled at S5P2 of every machine cycle and then their corresponding interrupt flags IEx will be set or re-
set. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has oc-
curred. These flag values are polled only in the next machine cycle. If a request is active and all three
conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four ma-
chine cycles to be completed. Thus there is a minimum time of five machine cycles between the inter-
rupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the instruc-
tion being executed, then an additional delay is introduced. The maximum response time (if no other
interrupt is in service) occurs if the device is performing a write to IE, IP and then executes a MUL or
DIV instruction.
13.5 Interrupt Inputs
Since the external interrupt pins are sampled once each machine cycle, an input high or low should
hold for at least 6 CPU Clocks to ensure proper sampling. If the external interrupt is high for at least
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