RM0365 Datasheet, PDF (95/1076 Pages) STMicroelectronics – This reference manual targets application developers

Flexible memory controller (FMC)
RM0365
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see Section 7.5.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 19) and support
for wait management (for PSRAM and NOR Flash accessed in burst mode).
Table 19. Programmable NOR/PSRAM access parameters
Parameter
Function
Access mode
Unit
Min.
Address
setup
Duration of the address
setup phase
Asynchronous
AHB clock cycle
(HCLK)
0
Address hold
Duration of the address hold
phase
Asynchronous,
muxed I/Os
AHB clock cycle
(HCLK)
1
Data setup
Duration of the data setup
phase
Asynchronous
AHB clock cycle
(HCLK)
1
Bust turn
Duration of the bus
turnaround phase
Asynchronous and
synchronous
read/write
AHB clock cycle
(HCLK)
0
Clock divide
ratio
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Synchronous
AHB clock cycle
(HCLK)
2
Data latency
Number of clock cycles to
issue to the memory before
the first data of the burst
Synchronous
Memory clock
cycle (CLK)
2
Max.
15
15
256
15
16
17
7.5.1
Note:
External memory interface signals
Table 20, Table 21 and Table 22 list the signals that are typically used to interface with NOR
Flash memory, SRAM and PSRAM.
The prefix “N” identifies the signals which are active low.
NOR Flash memory, non-multiplexed I/Os
Table 20. Non-multiplexed I/O NOR Flash memory
FMC signal name
I/O
Function
CLK
A[25:0]
D[15:0]
O
Clock (for synchronous access)
O
Address bus
I/O
Bidirectional data bus
NE[x]
O
Chip Select, x = 1..4
NOE
O
Output enable
NWE
NL(=NADV)
O
Write enable
O
Latch enable (this signal is called address
valid, NADV, by some NOR Flash devices)
NWAIT
I
NOR Flash wait input signal to the FMC
The maximum capacity is 512 Mbits (26 address lines).
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