RM0365 Datasheet, PDF (489/1076 Pages) STMicroelectronics – This reference manual targets application developers

RM0365
Advanced-control timers (TIM1)
20.3.15
Using the break function
The purpose of the break function is to protect power switches driven by PWM signals
generated with the TIM1 timer. The two break inputs are usually connected to fault outputs
of power stages and 3-phase inverters. When activated, the break circuitry shuts down the
PWM outputs and forces them to a predefined safe state.
When using the break functions, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 116: Output control bits for
complementary OCx and OCxN channels with break feature on page 531 for more details.
The source for BRK can be:
• An external source connected to the BKIN pin
• An internal source: COMP4 output
The source for BRK_ACTH can be internal only:
– A clock failure event generated by the CSS. For further information on the CSS,
refer to Section 10.2.7: Clock security system (CSS)
– A PVD output
– SRAM parity error signal
– Cortex M4 LOCKUP (Hardfault) output
– COMPx output, x = 1,2, and 6
The source for BRK2 can be:
• An external source connected to the BKIN2 pin
• An internal source coming from COMPx output, x = 1, 2, 4 or 6
If there are several break sources, the resulting break signal will be an OR between all the
input signals.
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break functions by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break
input polarities can be selected by configuring the BKP and BKP2 bits in the same register.
BKEx and BKPx can be modified at the same time. When the BKEx and BKPx bits are
written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently,
it is necessary to wait 1 APB clock period to correctly read back the bit after the write
operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.
The break can be generated by any of the break inputs (BRK, BRK2, BRK_ACTH), BRK
and BRK2 have:
– Programmable polarity (BKPx bit in the TIMx_BDTR register)
– Programmable enable bit (BKEx in the TIMx_BDTR register)
– Programmable filter (BKxF[3:0] bits in the TIMx_BDTR register) to avoid spurious
events.
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