RM0365 Datasheet, PDF (665/1076 Pages) STMicroelectronics – This reference manual targets application developers

General-purpose timers (TIM15/16/17)
RM0365
Table 123. Output control bits for complementary OCx and OCxN channels with break feature
Control bits
Output states⁽¹⁾
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state
OCxN output state
X
0
Output Disabled (not driven by the timer: Hi-Z)
0
OCx=0
OCxN=0, OCxN_EN=0
0
0
Output Disabled (not driven
1
by the timer: Hi-Z)
OCxREF + Polarity
OCxN=OCxREF XOR CCxNP
OCx=0
0
1
1
X
X
1
OCxREF + Polarity
0
Output Disabled (not driven by
the timer: Hi-Z)
OCx=OCxREF XOR CCxP _OCxN=0
1
OCREF + Polarity + dead- Complementary to OCREF (not
time
OCREF) + Polarity + dead-time
1
0
1
Off-State (output enabled
with inactive state)
OCxREF + Polarity
OCx=CCxP
OCxN=OCxREF XOR CCxNP
1
1
OCxREF + Polarity
Off-State (output enabled with
0
OCx=OCxREF xor CCxP, ^{inactive state)}
OCx_EN=1
OCxN=CCxNP, OCxN_EN=1
0
X
X
Output Disabled (not driven by the timer: Hi-Z)
0
0
OCx=CCxP, OCxN=CCxNP
0
0
X
1
1
1
1
Off-State (output enabled with inactive state)
0
Asynchronously: OCx=CCxP, OCxN=CCxNP
Then if the clock is present: OCx=OISx and OCxN=OISxN
1
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.
Note:
The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and AFIO registers.
22.5.9 TIM15 counter (TIM15_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
CPY
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
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