RM0365 Datasheet, PDF (334/1076 Pages) STMicroelectronics – This reference manual targets application developers

RM0365
Analog-to-digital converters (ADC)
1. The watchdog comparison is performed on the raw converted data before any alignment calculation and
before applying any offsets (the data which is compared is not signed).
Note:
ADCy_AWDx_OUT signal output generation
Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT
(y=ADC number, x=watchdog number) which is directly connected to the ETR input
(external trigger) of some on-chip timers. Refer to the on-chip timers section to understand
how to select the ADCy_AWDx_OUT signal as ETR.
ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled:
• ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is
inside the programmed thresholds (It remains at 1 if the next guarded conversions are
still outside the programmed thresholds).
• ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS=1).
Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1)
has no influence on the generation of ADCy_AWDx_OUT.
AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag
remains at 1 if the software did not clear the flag).
Figure 91. ADCy_AWDx_OUT signal generation (on all regular channels)
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