RM0365 Datasheet, PDF (653/1076 Pages) STMicroelectronics – This reference manual targets application developers

General-purpose timers (TIM15/16/17)
RM0365
22.5.3 TIM15 slave mode control register (TIM15_SMCR)
Address offset: 0x08
31
Res.
15
Res.
Reset value: 0x0000 0000
30
29
28
27
26
25
Res. Res. Res. Res. Res. Res.
14
Res.
13
Res.
12
Res.
11
Res.
10
Res.
9
Res.
24
Res.
8
Res.
23
Res.
7
MSM
rw
22
Res.
21
Res.
20
Res.
6
5
4
TS[2:0]
rw
rw
rw
19
Res.
3
Res.
18
17
16
Res. Res. SMS[3]
rw
2
1
0
SMS[2:0]
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bits 16 SMS[3]: Slave mode selection - bit 3
Refer to SMS description - bits 2:0
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
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