RM0365 Datasheet, PDF (321/1076 Pages) STMicroelectronics – This reference manual targets application developers

Analog-to-digital converters (ADC)
RM0365
$'67$57
Figure 78. Single conversions of a sequence, hardware trigger
(2&
(26
75*;^
$'&VWDWH^
$'&B'5
5'<
&+
&+
&+
'
'
&+ 5($'< &+
&+
'
'
'
&+
'
&+
'
5'<
'
E\VZ
E\KZ
WULJJHUHG
LJQRUHG
,QGLFDWLYHWLPLQJV
1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
Figure 79. Continuous conversions of a sequence, hardware trigger
069
$'67$57
(2&
(26
$'673
75*[^
$'&^
$'&B'5
5'<
&+
&+
'
&+
'
&+
'
&+
'
&+
'
&+
'
&+
'
&+
6723
'
5'<
E\VZ
E\KZ
WULJJHUHG
1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
LJQRUHG
1RWLQVFDOHWLPLQJV
069
15.3.26 Data management
Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH,
ALIGN)
Data and alignment
At the end of each regular conversion channel (when EOC event occurs), the result of the
converted data is stored into the ADCx_DR data register which is 16 bits wide.
At the end of each injected conversion channel (when JEOC event occurs), the result of the
converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits
wide.
The ALIGN bit in the ADCx_CFGR register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 80, Figure 81, Figure 82
and Figure 83.
321/1077
DocID025202 Rev 4