RM0365 Datasheet, PDF (183/1076 Pages) STMicroelectronics – This reference manual targets application developers

RM0365
Reset and clock control (RCC)
causes a switch of the system clock to the HSI oscillator and the disabling of the HSE
oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock
when the failure occurs, the PLL is disabled too.
10.2.8
ADC clock
The ADC clock is derived from the PLL output. It can reach 72 MHz and can be divided by
the following prescalers values: 1, 2, 4, 6, 8,10,12,16, 32, 64, 128 or 256. It is asynchronous
to the AHB clock. Alternatively, the ADC clock can be derived from the AHB clock of the
ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor
is configured using the CKMODE bit fields in the ADCx_CCR.
If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’.
10.2.9
RTC clock
The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR). This
selection cannot be modified without resetting the RTC domain. The system must always be
configured so as to get a PCLK frequency greater than or equal to the RTCCLK frequency
for a proper operation of the RTC.
The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock:
– The RTC continues to work even if the V_DD supply is switched off, provided the
V_BAT supply is maintained.
• If LSI is selected as the RTC clock:
– The RTC state is not guaranteed if the V_DD supply is powered off.
• If the HSE clock divided by 32 is used as the RTC clock:
– The RTC state is not guaranteed if the V_DD supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.8 V domain).
10.2.10 Timers (TIMx) clock
APB clock source
The timers clock frequencies are automatically defined by hardware. There are two cases:
1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
frequency as that of the APB domain.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
PLL clock source
A clock issued from the PLL (PLLCLKx2) can be selected for TIMx (x = 1 on the
STM32F302xB/C; x = 1, 15, 16 and 17 on the STM32F302x6/8). This configuration allows to
feed TIMx with a frequency up to 144 MHz when the system clock source is the PLL.
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