STE2002 Datasheet, PDF (43/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
ELECTRICAL CHARACTERISTICS (continued)
AC OPERATION
(V_DD1 = 1.7 to 3.6V; V_DD2 = 1.75 to 4.2V; V_ss1,2 = 0V; V_LCD = 4.5 to 11V; T_amb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
SERIAL INTERFACE
T_CYC Clock Cycle SCLK
V_DD1 = 1.7V; Write; note 2, 6
150
ns
T_PWH1 SCLK pulse width HIGH
60
ns
T_PWL1 SCLK Pulse width LOW
60
ns
T_S2 SCE setup time
30
ns
T_H2 SCE hold time
50
ns
T_PWH2 SCE minimum high time
50
ns
T_S3 SD/C setup time
30
ns
T_H3 SD/C hold time
40
ns
T_S4 SDIN setup time
30
ns
T_H4 SDIN hold time
40
ns
T_S5 SOUT Access Time
100
ns
T_H5 SOUT Disable Time vs. SCLK
100
ns
T_H6 SOUT Disable Time vs. SCE
100
ns
Figure 52. Serial interface Timing
CS
D/C
SCLK
SDIN
SOUT
tS2
tS3
tH3
tPWL1
tWH1
tS4
tH4
tS5
tH5
tH2
tPWH2
tCYC
tS2
tH6
LR0001
Notes: 1.
F_{fra m e}
=
f_--o---s---c-
960
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V_IL and V_IH with
an input voltage swing of VSS to VDD
3. Cb is the capacitive load for each bus line.
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. C_VLCD is the filtering Capacitor on VLCDOUT
6. T_rise and T_fall (30%-70%) = 10 ns
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