STE2002 Datasheet, PDF (10/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
Figure 6. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)¹
0
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
124 125 126 127
Figure 7. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)¹
0
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
124 125 126 127
Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)¹
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
127
126
125
124
3
2
1
0
Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)¹
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
127 126
125
124
1. X Carriage=127; Y-Carriage = 12
3
2
1
0
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