STE2002 Datasheet, PDF (41/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
ELECTRICAL CHARACTERISTICS
AC OPERATION
(V_DD1 = 1.7 to 3.6V; V_DD2 = 1.75 to 4.2V; V_ss1,2 = 0V; V_LCD = 4.5 to 11V; T_amb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
I²C BUS INTERFACE (See note 4)
F_SCL SCL Clock Frequency
Fast Mode
DC
400
kHz
High Speed Mode; Cb=100pF
DC
(max);VDD1=2
3.4
MHz
High Speed Mode; Cb=400pF
DC
(max); VDD1=2
1.7
MHz
Fast Mode; VDD1=1.7V
400 KHz
T_SU;STA Set-up time (repeated) START Note 2, 3, Cb=100pF
160
ns
condition
T_HD;STA Hold time (repeated) START
Note 2, 3, Cb=100pF
160
ns
condition
T_LOW LOW period of the SCLH clock Note 2, 3, Cb=100pF
160
ns
T_HIGH HIGH period of the SCLH clock Note 2, 3, Cb=100pF
60
ns
T_SU;DAT Data set-up time
Note 2, 3, Cb=100pF
10
ns
T_HD;DAT Data hold time
Note 2, 3; Cb=100pF
40
ns
T_r;CL Rise time of SCLH signal
Note 2, 3; Cb=100pF
10
ns
T_rCL1 Rise time of SCLH signal after a Note 2, 3, Cb=100pF
10
ns
repeated START condition and
after an acknowledge bit
T_fCL Fall time of SCLH signal
Note 2, 3, Cb=100pF
10
ns
T_rDA Rise time of SDAH signal
Note 2, 3, 4, Cb=100pF
10
ns
T_fDA Fall time of SDAH signal
Note 2, 3, 4, Cb=100pF
10
80
ns
T_rDA Rise time of SDAH signal
Note 2, 3, 4, Cb=400pF
20
ns
T_fDA Fall time of SDAH signal
Note 2, 3, 4, Cb=400pF
20
160
ns
T_SU;STO Set-up time for STOP condition Note 2, 3, Cb=100pF
160
ns
C_b Capacitive load for SDAH and
SCLH
100
400
pF
C_b Capacitive load for SDAH + SDA
line and SCLH + SCL line
400
pF
Figure 49. I²C-bus timings
Sr
t_fDA
t_rDA
Sr P
SDAH
t_SU;STA
t_HD;DAT
t_HD;STA
t_SU;DAT
SCLH
t_fCL
t_rCL
= MCS current source pull-up
= Rp resistor pull-up
t_HIGH t_LOW
trCL1
(1)
t_LOW t_HIGH
trCL1
(1)
D00IN1153
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