STE2002 Datasheet, PDF (22/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
the second is a data byte (fig 31). The Co bit is the command MSB and defines if after this command will follow
one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0
Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/
C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following
data byte will be stored in the data RAM at the location specified by the data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2002 Display
RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every
byte written and in the end points to the last RAM location written.
Every byte must be acknowledged by all addressed units.
Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent
during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 31. Communication Protocol
WRITE MODE
STE2002 ACK
STE2002 ACK
STE2002 ACK
STE2002 ACK
STE2002 ACK
SS
S 0 1 1 1 1 A A 0 A 1 DC Control Byte A DATA Byte A 0 DC Control Byte A DATA Byte A P
10
R/W Co
SLAVE ADDRESS
READ MODE
STE2002 ACK
COMMAND WORD
MASTER ACK
Co
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
SS
S0 1 1 1 1AA1A
10
SSR
P
0 1 1 1 1AA /
CD0 _{0 0 0 0 0 A}
1 0W
oC
R/W
STE2002
CONTROL BYTE
SLAVE ADDRESS
SERIAL INTERFACE
The STE2002 serial Interface is a bidirectional link between the display driver and the application supervisor.
It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the peripheral
enable (SCE) and one for mode selection (SD/C).
The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral
power consumption is zero. While SCE pin is high the serial interface is kept in reset.
The STE2002 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-
ter.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the
eighth SCLK clock pulse during every byte transfer.
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