STE2002 Datasheet, PDF (1/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
s 104 x 128 bits Display Data RAM
s Programmable MUX rate
s Programmable Frame Rate
s X,Y Programmable Carriage Return
s Dual Partial Display Mode
s Row by Row Scrolling
s Automatic data RAM Blanking procedure
s Selectable Input Interface:
• I²C Bus Fast and Hs-mode (read and write)
• Parallel Interface (read and write)
• Serial Interface (read and write)
s Fully Integrated Oscillator requires no external
components
s CMOS Compatible Inputs
s Fully Integrated Configurable LCD bias voltage
generator with:
• Selectable multiplication factor (up to 6X)
• Effective sensing for High Precision Output
• Eight selectable temperature compensation
coefficients
s Designed for chip-on-glass (COG) applications
s Low Power Consumption, suitable for battery
operated systems
s Logic Supply Voltage range from 1.7 to 3.6V
s High Voltage Generator Supply Voltage range
from 1.75 to 4.2V
s Display Supply Voltage range from 4.5 to 11V
s Backward Compatibility with STE2001
DESCRIPTION
The STE2002 is a low power CMOS LCD controller
driver. Designed to drive a 81 rows by 128 columns
graphic display, provides all necessary functions in a
single chip, including on-chip LCD supply and bias
voltages generators, resulting in a minimum of exter-
nals components and in a very low power consump-
tion. The STE2002 features three standard interfaces
(Serial, Parallel & I²C) for ease of interfacing with the
host mcontroller.
Type
Ordering Number
Bumped Wafers
STE2002DIE1
Bumped Dice on Waffle Pack
STE2002DIE2
Figure 1. Block Diagram
CO to C127
R0 to R80 ICON
OSC_IN
OSC_OUT
VLCDIN
VLCDSENSE
VLCDOUT
RES
VSSAUX
VDD1,2
V_SS
SEL1,2
SA1
OSC
TIMING
GENERATOR
COLUMN
DRIVERS
ROW
DRIVERS
BIAS VOLTAGE
GENERATOR
CLOCK
DATA
LATCHES
SHIFT
REGISTER
HIGH VOLTAGE
GENERATOR
RESET
DATA
REGISTER
104 x 128
RAM
SCROLL
LOGIC
TEST
INSTRUCTION
REGISTER
DISPLAY
CONTROL
LOGIC
TEST_1_14
ICON_MODE
EXT
BSY_FLG
I2CBUS
PARALLEL
SERIAL
SOUT
SAO SCL SDA_IN SDA_OUT DB0 to DB7 E R/W PD/C SCE SDIN SCLK SD/C
September 2002
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