STE2002 Datasheet, PDF (12/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
Figure 14. Data RAM Byte organization with D0 = 0
MSB
LSB
0
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
124 125 126 127
Figure 15. Data RAM Byte organization with D0 = 1
LSB
MSB
0
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
124 125 126 127
Figure 16. Memory Rows vs. Row drivers mapping with MY=0, MUX81, ICON MODE=0,1
ROW DRIVER ROW DRIVER
ICON MODE=1 ICON MODE=0
PHYSICAL MEMORY ROW
0123
R0
R0
ROW 0
R1
R1
ROW 1
R2
R2
ROW 2
R3
R3
ROW 3
124 125 126 127
Y-CARRIAGE
R 79
R 80
ICON
R 79
ROW 79
R 80
ROW 80
ICON ROW
Figure 17. Memory Rows vs. Row drivers mapping with MY=0, MUX 81, SCROLL POINTER = +3, ICON MODE=1
ROW DRIVER
ICON MODE=1
R0
R1
R2
R3
PHYSICAL MEMORY ROW
0123
ROW 0
ROW 1
ROW 2
ROW 3
124 125 126 127
R 76
R 77
R 78
R 79
R 80
ICON
ROW 79
ROW 80
Y-CARRIAGE
ICON ROW
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