STE2002 Datasheet, PDF (18/51 Pages) STMicroelectronics – 81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2002
Power Down (PD = 1)
When at Power Down, all LCD outputs are kept at V_SS (display off). Bias generator and V_LCD generator
are OFF (V_LCDOUT output is discharged to V_SS, and then is possible to disconnect V_LCDOUT). The internal
Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.
Memory Blanking Procedure
This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener-
ated in memory when starting up the device. This instruction substitutes (128X13) single "write" instruc-
tions. It is possible to program "Memory Blanking Procedure" only under the following conditions:
- PD bit = 0
The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is
running). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be
programmed for a period equivalent to 128X13 internal write cycles (128X13X1/fclock). The start of Mem-
ory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge
for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I²C
interface).
Checker Board Procedure
This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers, who
can now simply obtain complex module test configuration by means of a single instruction. It is possible to pro-
gram "Checker Board Procedure" only under the following conditions:
- PD bit = 0
The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running.
Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for
a period equivalent to 128X13 internal write cycles (128X13X1/fclock). The start of Memory blanking procedure
will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last
SCLK rising edge for the Serial interface, last SCL rising edge for the I²C interface).
Scrolling function
The STE2002 can scroll the graphics display in units of raster-rows. The scrolling function is achieved
changing the correspondence between the rows of the logical memory map and the output row drivers.
The scroll function doesn't affect the data ram content. It is only related to the visualization process. The
information output on the drivers is related to the row reading sequence (the 1st row read is output on R0,
the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially in-
creased or decreased. After every scrolling command the offset between the memory address and the
memory scanning pointer is increased or decreased by one. The offset range changes in accordance with
MUX Rate. After 80th/81th scrolling commands in MUX 81 mode, or after the 64th/65th scrolling com-
mands in mux 65 mode, or after 48nd/49rd scrolling command in MUX 49 mode, or after 32nd/33rd scroll-
ing command in MUX 33 mode, the offset between the memory address and the memory scanning pointer
is again zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory ad-
dress and the memory scanning pointer
The Icon Row is not scrolled if ICON MODE =1. If ICON MODE=0 the last row is like a general purpose
row and it is scrolled as other rows.
If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top
down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled
from bottom-up.
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