H3LIS100DL Datasheet, PDF (34/38 Pages) STMicroelectronics – 8-bit data output

Register description
H3LIS100DL
7.18 INT2_SRC (35h)
Table 49. INT2_SRC register
0
IA
ZH
ZL
YH
YL
XH
XL
Table 50. INT2_SRC description
Interrupt active. Default value: 0
IA
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
ZH
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
ZL
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
YH
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
YL
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
XH
(0: no interrupt, 1: X high event has occurred)
X Low. Default value: 0
XL
(0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read-only register.
Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2
pin) and allows the refresh of data in the INT2_SRC register if the latched option is chosen.
7.19
INT2_THS (36h)
Table 51. INT2_THS register
0
THS6
THS5
THS4
THS3
THS2
THS6 - THS0
Table 52. INT2_THS description
Interrupt 2 threshold. Default value: 000 0000
THS1
THS0
7.20
INT2_DURATION (37h)
Table 53. INT2_DURATION register
0
D6
D5
D4
D3
D2
D1
D0
D6 - D0
Table 54. INT2_DURATION description
Duration value. Default value: 000 0000
The D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized.
Duration time steps and maximum values depend on the ODR chosen.
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