H3LIS100DL Datasheet, PDF (32/38 Pages) STMicroelectronics – 8-bit data output

Register description
H3LIS100DL
7.14 INT1_SRC (31h)
Table 40. INT1_SRC register
0
IA
ZH
ZL
YH
YL
XH
XL
Table 41. INT1_SRC description
Interrupt active. Default value: 0
IA
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
ZH
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
ZL
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
YH
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
YL
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
XH
(0: no interrupt, 1: X high event has occurred)
X low. Default value: 0
XL
(0: no interrupt, 1: X low event has occurred)
Interrupt 1 source register. Read-only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refresh of data in the INT1_SRC register if the latched option is chosen.
7.15
INT1_THS (32h)
Table 42. INT1_THS register
0
THS6
THS5
THS4
THS3
THS2
Table 43. INT1_THS description
THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000
THS1
THS0
7.16 INT1_DURATION (33h)
Table 44. INT1_DURATION register
0
D6
D5
D4
D3
D2
D1
D0
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