H3LIS100DL Datasheet, PDF (26/38 Pages) STMicroelectronics – 8-bit data output

Register description
H3LIS100DL
Table 19. Power mode and low-power output data rate configurations
PM2
PM1
PM0
Power mode selection
Output data rate [Hz]
ODR_LP
0
0
0
Power-down
--
0
0
1
Normal mode
ODR
0
1
0
Low power
0.5
0
1
1
Low power
1
1
0
0
Low power
2
1
0
1
Low power
5
1
1
0
Low power
10
7.3
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Table 20. Normal mode output data rate configurations and low-pass cutoff
frequencies
DR1⁽¹⁾
DR0⁽¹⁾
Output data rate [Hz]
ODR
Low-pass filter cutoff
frequency [Hz]
0
0
50
37
0
1
100
74
1
0
400
292
1. “11” bit configuration is not allowed and may cause incorrect device functionality
CTRL_REG2 (21h)
BOOT
HPM1
Table 21. CTRL_REG2 register
HPM0
FDS
HPen2 HPen1
HPCF1
HPCF0
BOOT
HPM1, HPM0
FDS
HPen2
HPen1
HPCF1,
HPCF0
Table 22. CTRL_REG2 description
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
High-pass filter mode selection. Default value: 00
(00: normal mode; Others: refer to Table 23)
Filtered data selection. Default value: 0
(0: internal filter bypassed; 1: data from internal filter sent to output register)
High-pass filter enabled for interrupt 2 source. Default value: 0
(0: filter bypassed; 1: filter enabled)
High-pass filter enabled for interrupt 1 source. Default value: 0
(0: filter bypassed; 1: filter enabled)
High-pass filter cutoff frequency configuration. Default value: 00
(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)
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