H3LIS100DL Datasheet, PDF (12/38 Pages) STMicroelectronics – 8-bit data output

Mechanical and electrical specifications
H3LIS100DL
2.3.2
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Symbol
Table 6. I²C slave timing values
Parameter
I²C standard mode ⁽¹⁾
Min.
Max.
I²C fast mode ⁽¹⁾
Min.
Max.
f_(SCL)
t_w(SCLL)
t_w(SCLH)
t_su(SDA)
t_h(SDA)
t_r(SDA) t_r(SCL)
t_f(SDA) t_f(SCL)
t_h(ST)
t_su(SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition
setup time
0
4.7
4.0
250
0.01
4
4.7
100
0
400
1.3
0.6
100
3.45
0.01
0.9
1000
20 + 0.1C_b ⁽²⁾
300
300
20 + 0.1C_b ⁽²⁾
300
0.6
0.6
t_su(SP)
STOP condition setup time
4
0.6
t_w(SP:SR)
Bus free time between STOP
and START condition
4.7
1.3
1. Data based on standard I²C protocol requirement, not tested in production.
2. C_b = total capacitance of one bus line, in pF.
Figure 4. I²C slave timing diagram
Unit
KHz
μs
ns
μs
ns
μs
6'$
67$57
W_I6'$ 
W_U6'$
W_VX6'$
WK6'$
6&/
WK67  WZ6&// 
WZ6&/+ 
WU6&/
WI6&/
5(3($7('
67$57
W_VX65 
WZ6365 
67$57
W_VX63 
6723
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
12/38
DocID027504 Rev 2