H3LIS100DL Datasheet, PDF (29/38 Pages) STMicroelectronics – 8-bit data output

H3LIS100DL
Register description
7.6
CTRL_REG5 (24h)
Table 30. CTRL_REG5 register
0
0
0
0
0
0
TurnOn1 TurnOn0
TurnOn1,
TurnOn0
Table 31. CTRL_REG5 description
Turn-on mode selection for sleep-to-wake function. Default value: 00.
The turn-on bits are used for turning on the sleep-to-wake function.
TurnOn1
0
1
Table 32. Sleep-to-wake configuration
TurnOn0
Sleep-to-wake status
0
Sleep-to-wake function is disabled
1
Turned on: The device is in low-power mode (ODR is defined in
CTRL_REG1)
Setting TurnOn[1:0] bits to 11, the “sleep-to-wake” function is enabled. When an interrupt
event occurs, the device is turned to normal mode, increasing the ODR to the value defined
in CTRL_REG1. Although the device is in normal mode, CTRL_REG1 content is not
automatically changed to “normal mode” configuration.
7.7
HP_FILTER_RESET (25h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to
0 g. This allows the settling time of the high-pass filter to be overcome.
7.8
REFERENCE (26h)
Ref7
Ref6
Table 33. REFERENCE register
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
Table 34. REFERENCE description
Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.
This register sets the acceleration value taken as a reference for the high-pass filter output.
When the filter is turned on (at least one of the FDS, HPen2, or HPen1 bits is equal to ‘1’)
and the HPM bits are set to “01”, filter-out is generated, taking this value as a reference.
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