MB84VD23381HJ Datasheet, PDF (37/56 Pages) SPANSION – 64M (X16) FLASH MEMORY & 16M (X16) Mobile FCRAM

MBVD23381HJ-70
• WRITE OPERATION (16M FCRAM)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE1r Write Setup Time
CE1r Write Hold Time
WE Setup Time
WE Hold Time
LB and UB Setup Time
LB and UB Hold Time
OE Setup Time
OE Hold Time
OE High to CE1r Low Setup Time
OE High to Address Hold Time
CE1r Write Pulse Width
WE Write Pulse Width
CE1r Write Recovery Time
WE Write Recovery Time
Data Setup Time
Data Hold Time
CE1r High Pulse Width
Symbol
tWC
tAS
tAH
tCS
tCH
tWS
tWH
tBS
tBH
tOES
tOEH
tOEH[ABS]
tOHCL
tOHAH
tCW
tWP
tWRC
tWR
tDS
tDH
tCP
Value
Unit
Min Max
80
—
ns
0
—
ns
35
—
ns
0
1000 ns
0
1000 ns
0
—
ns
0
—
ns
–5
—
ns
–5
—
ns
0
1000 ns
25
1000 ns
12
—
ns
–5
—
ns
–5
—
ns
45
—
ns
45
—
ns
20
—
ns
20
1000 ns
15
—
ns
0
—
ns
10
—
ns
Notes
*1
*2, *9
*2
*9
*3
*3, *4
*5
*6
*7
*1, *8
*1, *8, *9
*1, *10
*1, *3, *10
*10
*1 : Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR).
*2 : New write address is valid from either CE1r or WE is bought to High.
*3 : The tOEH is specified from end of tWC(Min). The tOEH(Min) is a reference value when the access time is
determined by tOE.
If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of
subtracting actual value from specified minimum value.
*4 : The tOEH(Max) is applicable if CE1r is kept at Low and both WE and OE are kept at High.
*5 : The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stays Low.
*6 : tOHCL(Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL(Min), WE Low must be asserted after tRC(Min) from CE1r Low.
In other words, read operation is initiated if tOHCL(Min) is not satisfied.
*7 : Applicable if CE1r stays Low after read operation.
*8 : tCW and tWP is applicable if write operation is initiated by CE1r and WE, respectively.
*9 : If write operation is terminated by WE followed by CE1r = H, the sum of actual tCS and tWP, and the sum of
actual tAS and tWP must be equal or greater than 60 ns. For example, if actual tWP is 45 ns, tCS and tAS must be
equal or greater than 15 ns.
*10 : tWRC and tWR is applicable if write operation is terminated by CE1r and WE, respectively.
In case CE1r is brought to High before satisfaction of tWR(Min), the tWRC(Min) is also applied.
36