MB84VD23381HJ Datasheet, PDF (36/56 Pages) SPANSION – 64M (X16) FLASH MEMORY & 16M (X16) Mobile FCRAM

MB84VD23381HJ-70
s 16M FCRAM CHARACTERISTICS FOR MCP
1. AC Characteristics
• READ OPERATION (16M FCRAM)
Parameter
Value
Symbol
Unit
Min Max
Notes
Read Cycle Time
tRC
80
—
ns
Chip Enable Access Time
tCE
—
60
ns
*1, *3
Output Enable Access Time
tOE
—
35
ns
*1
Address Access Time
tAA
—
60
ns
*1, *4
Output Data Hold Time
tOH
5
—
ns
*1
CE1r Low to Output Low-Z
tCLZ
5
—
ns
*2
OE Low to Output Low-Z
tOLZ
0
—
ns
*2
CE1r High to Output High-Z
tCHZ
—
20
ns
*2
OE High to Output High-Z
tOHZ
—
20
ns
*2
Address Setup Time to CE1r Low
tASC
–5
—
ns
*5
Address Setup Time to OE Low
tASO
25
tASO[ABS]
5
—
ns
—
ns
*3, *6
*7
LB / UB Setup Time to CE1r Low
tBSC
–5
—
ns
*5
LB / UB Setup Time to OE Low
tBSO
0
—
ns
Address Invalid Time
tAX
—
5
ns
*4, *8
Address Hold Time from CE1r Low
tCLAH
80
—
ns
*4
Address Hold Time from OE Low
tOLAH
45
—
ns
*4, *9
Address Hold Time from CE1r High
tCHAH
–5
—
ns
Address Hold Time from OE High
tOHAH
–5
—
ns
LB / UB Hold Time from CE1r High
tCHBH
–5
—
ns
LB / UB Hold Time from OE High
tOHBH
–5
—
ns
CE1r Low to OE Low Delay Time
tCLOL
25 1000 ns
*3, *6, *9, *10
OE Low to CE1r High Delay Time
tOLCH
45
—
ns
*9
CE1r High Pulse Width
tCP
10
—
ns
OE High Pulse Width
tOP
25 1000 ns
tOP[ABS]
10
—
ns
*6, *9, *10
*7
*1 : The output load is 30 pF with 1 TTL.
*2 : The output load is 5 pF.
*3 : The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of
both or either tASO or tCLOL is shorter than specified value.
*4 : Applicable only to A0, A1 and A2 when both CE1r and OE are kept at Low for the address access.
*5 : Applicable if OE is brought to Low before CE1r goes Low.
*6 : The tASO, tCLOL(Min) and tOP(Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of
subtracting actual value from specified minimum value.
For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(Min), during OE control
access (ie., CE1r stays Low), the tOE become tOE(Max) + tASO(Min) – tASO(actual).
*7 : The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access.
*8 : The tAX is applicable when all or two addresses among A0 to A2 are switched from previous state.
*9 : If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become
tRC(Min) – tCLOL(actual) or tRC(Min) – tOP(actual).
*10 : Maximum value is applicable if CE1r is kept at Low.
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