LAN9221_12 Datasheet, PDF (97/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
5.3.16 GPT_CNT-General Purpose Timer Current Count Register
Offset:
90h
Size:
This register reflects the current value of the GP Timer.
32 bits
BITS
DESCRIPTION
31-16 Reserved
15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
TYPE
RO
RO
DEFAULT
-
FFFFh
5.3.17 WORD_SWAP—Word Swap Control
Offset:
98h
Size:
32 bits
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN9221/LAN9221i. The LAN9221/LAN9221i always sends data from the Transmit Data
FIFO to the network so that the low order word is sent first, and always receives data from the network
to the Receive Data FIFO so that the low order word is received first.
BITS
DESCRIPTION
31:0 Word Swap. If this field is set to 00000000h, or anything except
0xFFFFFFFFh, the LAN9221/LAN9221i maps words with address bit A[1]=1
to the high order words of the CSRs and Data FIFOs, and words with
address bit A[1]=0 to the low order words of the CSRs and Data FIFOs. If
this field is set to 0xFFFFFFFFh, the LAN9221/LAN9221i maps words with
address bit A[1]=1 to the low order words of the CSRs and Data FIFOs, and
words with address bit A[1]=0 to the high order words of the CSRs and Data
FIFOs.
Note:
Word swap is used in conjunction with the mixed endian
functionality to determine the final byte ordering. Refer to Section
3.7.3, "Mixed Endian Support" for more information.
TYPE
R/W
NASR
DEFAULT
00000000h
SMSC LAN9221/LAN9221i
97
DATASHEET
Revision 2.9 (03-01-12)