LAN9221_12 Datasheet, PDF (35/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
CSRs and Status FIFOs
RX/TX Data FIFO Port
Access (addresses 00h to
3Ch)
RX/TX Data FIFO Direct
Access
(FIFO_SEL = 1)
FPORTEND
(H W _C FG [29])
FIFO Port Endian Ordering
Logic
Direct FIFO Access Endian
Ordering Logic
FSELEND
(H W _C FG [28])
WORD_SWAP
"WORD SWAP"
Logic
D[15:0]
(Host Data Bus)
Figure 3.8 LAN9221/LAN9221i Host Data Path Diagram
Data path operations for the various supported endianess and word swap configurations are illustrated
in Figure 3.9. Table 3.8, "Endian Ordering Logic Operation" illustrates the byte ordering applied by the
endian logic for each type of host access. This figure and table assume an internal byte ordering of 3-
2-1-0, where ‘3’ is the most significant byte (data[31:24]) and ‘0’ is the least significant byte (data[7:0]).
SMSC LAN9221/LAN9221i
35
DATASHEET
Revision 2.9 (03-01-12)