LAN9221_12 Datasheet, PDF (50/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
init
Last Buffer in
Packet
Idle
Check
available
FIFO
space
TX Status
Available
Read TX
Status
(optional)
Write
TX
Command
Write
Start
Padding
(optional)
Write
Buffer
Not Last Buffer
Figure 3.19 Simplified Host TX Flow Diagram
3.12.1
TX Buffer Format
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN9221/LAN9221i in the handling and processing of the associated
Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters
are included in the command structure. The following diagram illustrates the buffer format.
Revision 2.9 (03-01-12)
50
DATASHEET
SMSC LAN9221/LAN9221i