LAN9221_12 Datasheet, PDF (44/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
3.10.2.1
3.10.2.2
Note 3.4 The LAN9221/LAN9221i must always be read at least once after power-up, reset, or upon
return from a power-saving state, otherwise write operations will not function.
In system configurations where the PME signal is shared amongst multiple devices, the WUPS field
within the PMT_CTRL register can be read to determine which LAN9221/LAN9221i device is driving
the PME signal.
When the LAN9221/LAN9221i is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST
register will return the LAN9221/LAN9221i to the D0 state. Table 7.2, “Power Consumption Device and
System Components,” on page 141 and Table 7.2, “Power Consumption Device and System
Components,” on page 141, shows the power consumption values for each power state.
Note 3.5
When the LAN9221/LAN9221i is in a power saving state, a write of any data to the
BYTE_TEST register will wake-up the device. DO NOT PERFORM WRITES TO OTHER
ADDRRESSES while the READY bit in the PMT_CTRL register is cleared.
D1 Sleep
Power consumption is reduced in this state by disabling clocks to portions of the internal logic as
shown in Table 3.10. In this mode the clock to the internal PHY and portions of the MAC are still
operational. This state is entered when the host writes a '01' to the PM_MODE bits in the Power
Management (PMT_CTRL) register. The READY bit in PMT_CTRL is cleared when entering the D1
state.
Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly
enabled via the WOL_EN and PME_EN bits, the LAN9221/LAN9221i will assert the PME hardware
signal upon the detection of the wake-up frame or magic packet. The LAN9221/LAN9221i can also
assert the host interrupt (IRQ) on detection of a wake-up frame or magic packet. Upon detection, the
WUPS field in PMT_CTRL will be set to a 10b.
Note 3.6 The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the
setting of PME_EN.
Note 3.7
Wake-up frame and Magic Packet detection is automatically enabled when entering the D1
state. For wake-up frame detection, the wake-up frame filter must be programmed before
entering the D1 state (see Section 3.5, "Wake-up Frame Detection," on page 26). If used,
the host interrupt and PME signal must be enabled prior to entering the D1 state.
A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was
detected, will return LAN9221/LAN9221i to the D0 state and will reset the PM_MODE field to the D0
state. As noted above, the host is required to check the READY bit and verify that it is set before
attempting any other reads or writes of the device.
Note 3.8 The host must only perform read accesses prior to the ready bit being set.
Once the READY bit is set, the LAN9221/LAN9221i is ready to resume normal operation. At this time
the WUPS field can be cleared.
D2 Sleep
In this state, as shown in Table 3.10, all clocks to the MAC and host bus are disabled and the PHY is
placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY
(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The
PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,
the LAN9221/LAN9221i will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when
entering the D2 state.
Note 3.9 If carrier is present when this state is entered detection will occur immediately.
If properly enabled via the ED_EN and PME_EN bits, the LAN9221/LAN9221i will assert the PME
hardware signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will
be set to a 01b.
Revision 2.9 (03-01-12)
44
DATASHEET
SMSC LAN9221/LAN9221i