LAN9221_12 Datasheet, PDF (109/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
5.4.2 ADDRH—MAC Address High Register
Offset:
Default Value:
2
0000FFFFh
Attribute:
Size:
R/W
32 bits
The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address
0x06 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM. Section 5.4.3
details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the
Ethernet physical address.
BITS
31-16
15-0
DESCRIPTION
Reserved
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of
the LAN9221/LAN9221i device. The content of this field is undefined until loaded from the EEPROM
at power-on. The host can update the contents of this field after the initialization process has
completed.
SMSC LAN9221/LAN9221i
109
DATASHEET
Revision 2.9 (03-01-12)