LAN9221_12 Datasheet, PDF (135/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
6.8
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9221/LAN9221i will
write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access.
This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This
mode is useful when the host processor must increment its address when accessing the
LAN9221/LAN9221i. Timing is identical to a PIO write, and the FIFO_SEL signal has the same timing
characteristics as the address lines.
FIFO_SEL
A[2:1]
nCS, nWR
Data Bus
Figure 6.7 TX Data FIFO Direct PIO Write Timing
Note: The “Data Bus” width is 16 bits.
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
45
32
13
0
0
7
0
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
SMSC LAN9221/LAN9221i
135
DATASHEET
Revision 2.9 (03-01-12)