LAN9221_12 Datasheet, PDF (88/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

5.3.9
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
HW_CFG—Hardware Configuration Register
Offset:
74h
Size:
32 bits
Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section
3.12.8, "Stopping and Starting the Transmitter," on page 61 and Section 3.13.4, "Stopping and
Starting the Receiver," on page 66 for details on stopping the transmitter and receiver.
BITS
DESCRIPTION
31 Reserved
30 Reserved
29
28
27-25
FIFO Port Endian Ordering (FPORTEND). This control bit determines the
endianess of RX and TX data FIFO host accesses when accessed through
the RX/TX Data FIFO ports, including the alias addresses (any access from
00h to 3Ch). When this bit is cleared, data FIFO port accesses utilize little
endian byte ordering. When this bit is set, data FIFO port accesses utilize
big endian byte ordering. Please refer to section Section 3.7.3, "Mixed
Endian Support," on page 34 for more information on this feature.
Direct FIFO Access Endian Ordering (FSELEND). This control bit
determines the endianess of RX and TX data FIFO host accesses when
accessed using the FIFO_SEL signal. When this bit is cleared, FIFO_SEL
accesses utilize little endian byte ordering. When this bit is set, FIFO_SEL
accesses utilize big endian byte ordering. Please refer to section Section
3.7.3, "Mixed Endian Support," on page 34 for more information on this
feature.
Reserved
24 AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
23-21 Reserved
20
16-19
15-2
Must Be One (MBO). This bit must be set to “1” for normal device
operation.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 90 for more information.
Reserved
1
Soft Reset Timeout (SRST_TO). If a software reset is attempted when the PHY
is not in the operational state (RX_CLK and TX_CLK running), the reset will not
complete and the soft reset operation will timeout and this bit will be set to a ‘1’. The
host processor must correct the problem and issue another soft reset.
TYPE
RO
RO
R/W
NASR
R/W
NASR
RO
RO
RO
R/W
R/W
RO
RO
DEFAULT
-
-
0
0
-
AMDIX
Strap
Pin
0
5h
-
0
Revision 2.9 (03-01-12)
88
DATASHEET
SMSC LAN9221/LAN9221i