LAN91C111 Datasheet, PDF (91/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
INTMDIO:
Interrupt
Scheme Select
0 = No Multiple
Register Access
0 = No
Multiple
Register
Access
1 = Interrupt
Signaled With
MDIO Pulse
During Idle
1 = Interrupt
Signaled
With MDIO
Pulse During
Idle
0 = Interrupt
Not Signaled
On MDIO
0 = Interrupt
Not Signaled
On MDIO
Reserved:
Reserved for
Factory Use
9.8
Register 18. Status Output - Structure and Bit Definition
INT
LNKFAIL
LOSSSYNC
CWRD
R
R/LT
R/LT
R/LT
0
0
0
0
SSD
R/LT
0
ESD
R/LT
0
RPOL
R/LT
0
JAB
R/LT
0
SPDDET
R/LT
1
DPLXDET
R/LT
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
INT:
LNKFAIL:
LOSSSYNC:
CWRD:
Interrupt Detect
Link Fail Detect
Descrambler Loss of
Synchronization
Detect
Codeword Error
1 = Interrupt Bit(s)
Have Changed
Since Last Read
Operation.
0 = No Change
1 = Link Not
Detected
0 = Normal
1 = Descrambler
Has Lost
Synchronization
0 = Normal
1 = Invalid 4B5B
Code Detected On
Receive Data
0 = Normal
SMSC LAN91C111-REV B
91
DATASHEET
Revision 1.8 (07-13-05)