LAN91C111 Datasheet, PDF (71/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.19 Bank 2 - Pointer Register
OFFSET
6
NAME
POINTER REGISTER
TYPE
READ/WRITE
NOT EMPTY IS
A READ ONLY
BIT
SYMBOL
PTR
HIGH
BYTE
LOW
BYTE
RCV
0
0
AUTO
INCR.
0
0
READ
0
0
ETEN
NOT
EMPTY
0
0
POINTER LOW
0
0
POINTER HIGH
0
0
0
0
0
0
8.20
POINTER REGISTER - The value of this register determines the address to be accessed within the
transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR.
is set. The increment is by one for every byte access, by two for every word access, and by four for
every double word access. When RCV is set the address refers to the receive area and uses the
output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area
and uses the packet number at the Packet Number Register.
READ - Determines the type of access to follow. If the READ bit is high the operation intended is a
read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit
high, generates a pre-fetch into the Data Register for read purposes.
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than
the last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it
without affecting the process being interrupted. The Pointer Register should not be loaded until the
Data Register FIFO is empty. The NOT EMPTY bit of this register can be read to determine if the
FIFO is empty. On reads, if ARDY is not connected to the host, the Data Register should not be read
before 370ns after the pointer was loaded to allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
ETEN - When set enables EARLY Transmit underrun detection. Normal operation when clear.
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that
the FIFO is empty before loading a new pointer value. This is a read only bit.
Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
Bank 2 - Data Register
OFFSET
8 THROUGH
BH
NAME
DATA REGISTER
TYPE
SYMBOL
READ/WRITE
DATA
SMSC LAN91C111-REV B
71
DATASHEET
Revision 1.8 (07-13-05)