LAN91C111 Datasheet, PDF (128/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

t26
t26A
t13
PARAMETER
ARDY Low Pulse Width
Control Active to ARDY Low
Valid Data to ARDY High
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
MIN
TYP
MAX UNITS
100
150
ns
10
ns
10
ns
Clock
t12
t17
t22
nDATACS
W/nR
nCYCLE
Write Data
t20
a
nRDYRTN
t18
t14
t20
b
t15
t18
t12A
t17A
t22A
t20
c
Figure 14.5 Burst Write Cycles - nVLBUS=1
PARAMETER
t12
t12A
t14
t15
t17
t17A
t18
t20
t22
t22A
nDATACS Setup to LCLK Rising
nDATACS Hold After LCLK Rising
nRDYRTN Setup to LCLK Falling
nRDYRTN Hold after LCLK Falling
W/nR Setup to LCLK Falling
W/nR Hold After LCLK Falling
Data Setup to LCLK Rising (Write)
Data Hold from LCLK Rising (Write)
nCYCLE Setup to LCLK Rising
nCYCLE Hold After LCLK Rising
Revision 1.8 (07-13-05)
128
DATASHEET
MIN TYP MAX UNITS
20
ns
0
ns
10
ns
10
ns
15
ns
3
ns
15
ns
4
ns
5
ns
10
ns
SMSC LAN91C111-REV B