LAN91C111 Datasheet, PDF (129/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Clock
nDATACS
W/nR
nCYCLE
Read Data
nRDYRTN
t17 t12
t14
t19
a
b
t15
t12A
t17A
t19
c
Figure 14.6 Burst Read Cycles - nVLBUS=1
PARAMETER
t12
t12A
t14
t15
t17
t17A
t19
nDATACS Setup to LCLK Rising
nDATACS Hold after LCLK Rising
nRDYRTN Setup to LCLK Falling
nRDYRTN Hold after LCLK Falling
W/nR Setup to LCLK Falling
W/nR Hold After LCLK Falling
Data Delay from LCLK Rising (Read)
MIN TYP MAX UNITS
20
ns
0
ns
10
ns
10
ns
15
ns
3
ns
5
15
ns
SMSC LAN91C111-REV B
129
DATASHEET
Revision 1.8 (07-13-05)