LAN91C111 Datasheet, PDF (4/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table 0.1 LAN91C111 Datasheet Revision History (continued)
NAME
REVISION
LEVEL AND
DATE
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
Rev. 1.0
(07-01-02)
SECTION/FIGURE/ENTRY
CORRECTION
Section 8.5, "Bank 0 -
Transmit Control Register," on
page 57
Section 8.10, "Bank 0 -
Receive/Phy Control
Register," on page 61
Section 8.21, "Bank 2 -
Interrupt Status Registers," on
page 72
Figure 8.2 Interrupt
Structureon page 75
Add Description for FDUPLX bit.
Add Description for SPEED, DPLX, ANEG
bits.
Add Description for Interrupt Status and
Mask bits.
Modified Interrupt Structure Figure.
Chapter 9, "PHY MII
Registers ," on page 81
Changed bit name 0 to Reserved.
Section 9.10, "Register 20.
Reserved - Structure and Bit
Definition," on page 93
Section 10.2, "Typical Flow of
Events for Transmit (Auto
Release = 0)," on page 96
Section 10.3, "Typical Flow of
Events for Transmit (Auto
Release = 1)," on page 97
Reserved bits default at 00A0.
Modified Typical Flow of Event for TX.
Modified Typical Flow of Event for TX.
SMSC LAN91C111-REV B
4
DATASHEET
Revision 1.8 (07-13-05)