LAN91C111 Datasheet, PDF (78/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

8.25 Bank 3 - Early RCV Register
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
OFFSET
C
NAME
EARLY RCV REGISTER
TYPE
READ/WRITE
SYMBOL
ERCV
HIGH
BYTE
Reserved
0
0
0
0
0
0
0
0
LOW
BYTE
RCV
Reserved Reserved
DISCRD
ERCV THRESHOLD
0
0
0
1
1
1
1
1
8.26
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of
being received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status
register will be set to indicate that the packet was discarded. Otherwise, the packet will be received
normally and bit 0 set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing.
ERCV THRESHOLD - Threshold for ERCV interrupt. Specified in 64 byte multiples. Whenever the
number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD,
ERCV INT bit of the INTERRUPT STATUS REGISTER is set.
Bank 7 - External Registers
OFFSET
NAME
0
THROUG
H7
EXTERNAL REGISTERS
TYPE
SYMBOL
nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range
occurs.
HIGH
BYTE
EXTERNAL R/W REGISTER
LOW
BYTE
EXTERNAL R/W REGISTER
Revision 1.8 (07-13-05)
78
DATASHEET
SMSC LAN91C111-REV B