LAN91C111 Datasheet, PDF (62/142 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at
full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode. When
the ANEG bit = 1, this bit is ignored and duplex mode is determined by the outcome of the Auto-
negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register) when the
ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
ANEG – Auto-Negotiation mode select - The PHY is placed in Auto-Negotiation mode when the ANEG
bit and the ANEG_EN bit in PHY Register 0 (Control Register) both are set. When either of these bits
is cleared (0), the PHY is placed in manual mode.
WHAT DO YOU
WANT TO DO?
AUTO-
NEGOTIATION
CONTROL BITS
AUTO-NEGOTIATION ADVERTISEMENT
REGISTER
Try to Auto-Negotiate
to ……
ANEG
Bit
RPCR
(MAC
)
ANEG_E
N
Bit
Register 0
(PHY)
TX_FDX
Bit
Register
4
(PHY)
TX_HDX
Bit
Register
4
(PHY)
10_FDX
Bit
Register
4
(PHY)
10_HDX
Bit
Register
4
(PHY)
100 Full Duplex
1
1
100 Half Duplex
1
1
10 Full Duplex
1
1
10 Half Duplex
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
DUPLEX
MODE
CONTROL
FOR THE
MAC
SWFDUP
Bit
Transmit
Control
Register
(MAC)
1
0
1
0
WHAT DO YOU
WANT TO DO?
AUTO-
NEGOTIATION
CONTROL BITS
SPEED AND DUPLEX MODE CONTROL
FOR THE PHY
Try to Manually Set to
……
100 Full Duplex
100 Half Duplex
ANEG
Bit
ANEG_E
N
Bit
RPCR
(MAC
Bank
0
Offset
A)
Register 0
(PHY)
0
0
0
1
1
0
0
0
0
1
1
0
SPEED
Bit
RPCR
(MAC
Bank 0
Offset A)
1
1
X
1
1
X
DPLX
Bit
RPCR
(MAC
Bank 0
Offset A)
1
1
X
0
0
X
SPEED
Bit
Register
0
(PHY)
X
X
1
X
X
1
DPLX
Bit
Register
0
(PHY)
X
X
1
X
X
0
DUPLEX
MODE
CONTROL
FOR THE
MAC
SWFDUP
Bit
Transmit
Control
Register
(MAC)
1
1
1
0
0
0
Revision 1.8 (07-13-05)
62
DATASHEET
SMSC LAN91C111-REV B