LAN83C185 Datasheet, PDF (44/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

5.4.2
5.4.3
5.4.4
5.4.5
5.4.5.1
5.4.5.2
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Collision Detect
Datasheet
A collision is the occurrence of simultaneous transmit and receive operations. The COL output is
asserted to indicate that a collision has been detected. COL remains active for the duration of the
collision. COL is changed asynchronously to both RX_CLK and TX_CLK. The COL output becomes
inactive during full duplex mode.
COL may be tested by setting register 0, bit 7 high. This enables the collision test. COL will be asserted
within 512 bit times of TX_EN rising and will be de-asserted within 4 bit times of TX_EN falling.
In 10M mode, COL pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de-
assertion of TX_EN). This is the Signal Quality Error (SQE) signal and indicates that the transmission
was successful. The user can disable this pulse by setting bit 11 in register 27.
Isolate Mode
The PHY data paths may be electrically isolated from the MII by setting register 0, bit 10 to a logic
one. In isolation mode, the PHY does not respond to the TXD, TX_EN and TX_ER inputs. The PHY
still responds to management transactions.
Isolation provides a means for multiple PHYs to be connected to the same MII without contention
occurring. The PHY is not isolated on power-up (bit 0:10 = 0).
Link integrity Test
The LAN83C185 performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link
Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable
link status bit in Serial Management Register 1, and is driven to the LINKON LED.
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using internal signal called
DATA_VALID. When DATA_VALID is asserted the control logic moves into a Link-Ready state, and
waits for an enable from the Auto Negotiation block. When received, the Link-Up state is entered, and
the Transmit and Receive logic blocks become active. Should Auto Negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state, when the DATA_VALID is asserted.
Note that to allow the line to stabilize, the link integrity logic will wait a minimum of 330 µsec from the
time DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10Base-T mode, the link status is from the 10Base-T receiver logic.
Power-Down modes
There are 2 power-down modes for the Phy:
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the entire PHY, except the
management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset.
Energy Detect Power-Down
This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present
on the line the PHY is powered down, except for the management interface, the SQUELCH circuit and
the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from
100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and
Rev. 0.8 (11-16-04)
44
DATASHEET
SMSC LAN83C185