LAN83C185 Datasheet, PDF (12/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Chapter 3 Pin Description
Datasheet
3.1
This chapter describes in detail the functionality of each of the five main architectural blocks.
The term “block” defines a stand-alone entity on the floor plan of the chip.
I/O Signals
I – Input. Digital TTL levels.
O – Output. Digital TTL levels.
AI – Input. Analog levels.
AO – Output. Analog levels.
AI/O – Input or Output. Analog levels.
Note: Reset as used in the signal descriptions is defined as nRST being active low.
Configuration inputs are listed in parenthesis.
PIN NO.
SIGNAL NAME
41
TXD0
42
TXD1
39
TX_EN
35
RX_ER
(RXD4)
47
COL
32
RXD0
31
RXD1
44
TXD2
45
TXD3
Table 3.1 MII Signals
TYPE
DESCRIPTION
I
Transmit Data 0: Bit 0 of the 4 data bits that are accepted
by the PHY for transmission.
I
Transmit Data 1: Bit 1 of the 4 data bits that are accepted
by the PHY for transmission.
I
Transmit Enable: Indicates that valid data is presented
on the TXD[3:0] signals, for transmission.
O
Receive Error: Asserted to indicate that an error was
O
detected somewhere in the frame presently being
transferred from the PHY.
In Symbol Interface (5B Decoding) mode, this signal is the
MII Receive Data 4: the MSB of the received 5-bit symbol
code-group.
O
MII Collision Detect: Asserted to indicate detection of
collision condition.
O
Receive Data 0: Bit 0 of the 4 data bits that are sent by
the PHY in the receive path.
O
Receive Data 1: Bit 1 of the 4 data bits that are sent by
the PHY in the receive path.
I
Transmit Data 2: Bit 2 of the 4 data bits that are accepted
by the PHY for transmission.
I
Transmit Data 3: Bit 3 of the 4 data bits that are accepted
by the PHY for transmission.
Rev. 0.8 (11-16-04)
12
DATASHEET
SMSC LAN83C185