LAN83C185 Datasheet, PDF (40/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Table 5.43 Register 18 - Special Modes (continued)
Datasheet
ADDRESS
NAME
18.4:0
PHYAD
DESCRIPTION
MODE DEFAULT
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to Section 5.4.9.1, "Physical Address Bus -
PHYAD[4:0]," on page 46 for more details.
RW,
NASR
PHYAD
ADDRESS
NAME
20.15
READ
20.14
WRITE
20.13:11
20.10
Reserved
TEST MODE
20.9:5
20.4:0
READ
ADDRESS
WRITE
ADDRESS
Table 5.44 Register 20 - TSTCNTL
DESCRIPTION
MODE DEFAULT
When setting this bit to “1”, the content of the register RW
0
that is selected by the READ ADDRESS will be
latched to the TSTREAD1/2 registers. This bit is self-
cleared.
When setting this bit to “1”, the register that is selected RW
0
by the WRITE ADDRESS is going to be written with
the data from the TSTWRITE register. This bit is self-
cleared.
Enable the Testability/Configuration mode:
0 - Testability/Configuration mode disabled
1 - Testability/Configuration mode enabled
RW
0
The address of the Testability/Configuration register RW
0
that will be latched into the TSTREAD1 and
TSTREAD2 registers
The address of the Testability/Configuration register RW
0
that will be written.
ADDRESS
NAME
21.15:0
READ_DATA
Table 5.45 Register 21 - TSTREAD1
DESCRIPTION
MODE DEFAULT
When reading registers with a size of less then 16
RO
0
bits, this register contain the register data, starting
from bit 0.
When reading registers with a size of more then 16
bits, this register contain the less significant 16 bits of
the register data.
ADDRESS
NAME
22.15:0
READ_DATA
Table 5.46 Register 22 - TSTREAD2
DESCRIPTION
When reading registers with a size of less then 16
bits, this register clears to zeros.
When reading registers with a size of more then 16
bits, this register contains the most significant bits of
the register data, starting from the 16^th bit.
MODE DEFAULT
RO
0
Rev. 0.8 (11-16-04)
40
DATASHEET
SMSC LAN83C185