LAN83C185 Datasheet, PDF (27/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 4.4 and Figure 4.5.
The timing relationships of the MDIO signals are further described in Section 6.1, "Serial
Management Interface (SMI) Timing," on page 51.
MDC
MDI0
Read Cycle
32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
Preamble
Start of
Frame
OP
Code
PHY Address
Register Address
Turn
Around
...
...
Data
D1 D0
Data To Phy
Data From Phy
Figure 4.4 MDIO Timing and Frame Structure - READ Cycle
MDC
MDIO
Write Cycle
32 1's 0 1 0 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
Preamble
Start of
Frame
OP
Code
PHY Address
Register Address
Turn
Around
...
...
Data
D1 D0
Data To Phy
Figure 4.5 MDIO Timing and Frame Structure - WRITE Cycle
SMSC LAN83C185
27
DATASHEET
Rev. 0.8 (11-16-04)