LAN83C185 Datasheet, PDF (26/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

4.7.2
4.7.3
4.7.4
4.8
4.8.1
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Re-starting Auto-negotiation
Datasheet
Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also re-
start if the link is broken at any time. A broken link is caused by signal loss. This may occur because
of a cable break, or because of an interruption in the signal transmitted by the Link Partner. Auto-
negotiation resumes in an attempt to determine the new link configuration.
If the management entity re-starts Auto-negotiation by writing to bit 9 of the control register, the
LAN83C185 will respond by stopping all transmission/receiving operations. Once the break_link_timer
is done, in the Auto-negotiation state-machine (approximately 1200ms) the auto-negotiation will re-
start. The Link Partner will have also dropped the link due to lack of a received signal, so it too will
resume auto-negotiation.
Disabling Auto-negotiation
Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its
speed of operation to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex).
The speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled.
Half vs. Full Duplex
Half Duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)
protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds
to both transmit and receive activity. In this mode, If data is received while the PHY is transmitting,
a collision results.
In Full Duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS
responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is
disabled.
PHY Management Control
The Management Control module includes 3 blocks:
■ Serial Management Interface (SMI)
■ Management Registers Set
■ Interrupt
Serial Management Interface (SMI)
The Serial Management Interface is used to control the LAN83C185 and obtain its status. This
interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as
“vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (7 to 15) will
be read as hexadecimal “FFFF”.
At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and
MDC is the clock.
A special feature (enabled by register 17 bit 3) forces the PHY to disregard the PHY-Address in the
SMI packet causing the PHY to respond to any address. This feature is useful in multi-PHY
applications and in production testing, where the same register can be written in all the PHYs using a
single write transaction.
The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO
signal receives serial data (commands) from the controller SMC, and sends serial data (status) to
the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time
between edges.
Rev. 0.8 (11-16-04)
26
DATASHEET
SMSC LAN83C185