LAN83C185 Datasheet, PDF (14/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 3.4 Configuration Inputs
PIN NO.
SIGNAL NAME
2
PHYAD4
20
PHYAD3
19
PHYAD2
17
PHYAD1
16
PHYAD0
6
MODE2
5
MODE1
4
MODE0
10
TEST1
9
TEST0
12
REG_EN
TYPE
DESCRIPTION
I
PHY Address Bit 4: set the default address of the PHY.
I
PHY Address Bit 3: set the default address of the PHY.
I
PHY Address Bit 2: set the default address of the PHY.
I
PHY Address Bit 1: set the default address of the PHY.
I
PHY Address Bit 0: set the default address of the PHY.
I
PHY Operating Mode Bit 2: set the default MODE of the
PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on
page 47 for the MODE options.
I
PHY Operating Mode Bit 1: set the default MODE of the
PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on
page 47 for the MODE options.
I
PHY Operating Mode Bit 0: set the default MODE of the
PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on
page 47 for the MODE options.
I
Test Mode Select 1: Must be left floating.
I
Test Mode Select 0: Must be left floating.
I
Internal +1.8V Regulator Enable:
+3.3V – Enables internal regulator.
0V – Disables internal regulator.
PIN NO.
SIGNAL NAME
46
nINT
25
nRST
23
CLKIN/XTAL1
22
XTAL2
11
CLK_FREQ
64
NC1
3
GPO2
2
GPO1
Rev. 0.8 (11-16-04)
Table 3.5 General Signals
TYPE
DESCRIPTION
OD
LAN Interrupt – Active Low output.
I
External Reset – input of the system reset. This signal is
active LOW.
I
Clock Input – 25 MHz external clock or crystal input.
O
Clock Output – 25 MHz crystal output.
I
Clock Frequency – define the frequency of the input
clock CLKIN
0 – Clock frequency is 25 MHz.
1 – Reserved.
This input needs to be held low continuously, during and
after reset. This pin should be pulled-down to VSS via a
pull-down resistor.
No Connect
O
General Purpose Output 2 – General Purpose Output
signal Driven by bits in registers 27 and 31.
O
General Purpose Output 1 – General Purpose Output
signal Driven by bits in registers 27 and 31.
(Muxed with PHYAD4 signal)
14
DATASHEET
SMSC LAN83C185