LAN83C185 Datasheet, PDF (41/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.47 Register 23 - TSTWRITE
ADDRESS
NAME
23.15:0
WRITE_DATA
DESCRIPTION
This field contains the data that will be written to a
specific register on the “Programming” transaction.
MODE DEFAULT
RW
0
Table 5.48 Register 27 - Special Control/Status Indications
ADDRESS
NAME
27.15:13
27.12
Reserved
SWRST_FAST
27:11
SQEOFF
27:10
VCOOFF_LP
27.9
Reserved
27.8
Reserved
27.7
Reserved
27.6
Reserved
27.5
Reserved
27.4
XPOL
27.3:0
AUTONEGS
DESCRIPTION
MODE DEFAULT
RW
1 = Accelerates SW reset counter from 256 ms to 10 RW
us for production testing.
Disable the SQE test (Heartbeat):
0 - SQE test is enabled.
1 - SQE test is disabled.
RW,
NASR
Forces the Receive PLL 10M to lock on the reference
clock at all times:
0 - Receive PLL 10M can lock on reference or line as
needed (normal operation)
1 - Receive PLL 10M is locked on the reference clock.
In this mode 10M data packets cannot be received.
RW,
NASR
Write as 0. Ignore on read.
RW
Write as 0. Ignore on read.
RW
Write as 0. Ignore on read
RW
Write as 0. Ignore on read.
RW
Write as 0. Ignore on read.
RW
Polarity state of the 10Base-T:
RO
0 - Normal polarity
1 - Reversed polarity
Auto-negotiation “ARB” State-machine state
RO
0
0
0
0
0
0
0
0
0
1011
Table 5.49 Register 28 - Special Internal Testability Controls
ADDRESS
NAME
28.15:0
Reserved
DESCRIPTION
Do not write to this register. Ignore on read.
MODE DEFAULT
RW
N/A
Table 5.50 Register 29 - Interrupt Source Flags
ADDRESS
NAME
29.15:8
Reserved
DESCRIPTION
Ignore on read.
29.7
INT7
1 = ENERGYON generated
0 = not source of interrupt
SMSC LAN83C185
41
DATASHEET
MODE DEFAULT
RO/
0
LH
RO/
0
LH
Rev. 0.8 (11-16-04)